The present invention relates to an information recording and reproducing method based on a sampled servo system for a recording medium on which servo areas and data areas are formed alternately along tracks, wherein information is written and read out in the data areas using a light beam while the tracking control takes place in response to the servo signal retrieved intermittently from the servo areas, and more particularly to an information recording and reproduction method based on sampled clocking in which a clock signal is produced from the signal preformatted in the servo areas and information is written and read out in accordance with the clock signal. The invention also relates to an apparatus for carrying out this method and to a recording medium on which information is written and read out on the basis of this method.
Generally, conventional CD (Compact Disc) players and optical disk file units have been controlled for light spot tracking and focusing according to a continuous servo system. Recently, a different optical disk file system based on sampled value control has been proposed (which hereinafter will be termed "sampled servo system"). This system will first be explained briefly on FIGS. 1 and 2A-2B. In FIG. 1, an optical disk 1 of sampled servo system has its tracks each partitioned into segments 4 of 1000-2000 in number, and each servo segment 4 is divided into a servo area 2 and data area 3 as shown in FIG. 2A. Accordingly, the optical disk has on its information recording surface an alternate disposition of servo areas and data areas on each circular track. In the sampled servo system, the tracking signal is produced from a pair of wobbled pits 5 formed on both sides of the track center 7 within the servo area 2, and a clock signal is produced from a clock pit 6 formed at the track center 7 within the servo area 2. These wobbled pits 5 and clock pit 6 are preformatted in the servo area, and they provide an intermittent servo signal and clock signal for use in writing or reading data in the data area 3. Because of the complete separate arrangement for the data area and servo area, which allows the servo signal to be free from the interference of the recording data during the recording or reproducing operation, the sampled servo system is advantageous in having a stable servo system and a simple optical system. The sampled servo system is described in the Japanese periodical "Nikkei Electronics", No. 410, pp. 165-170, published on Dec. 15, 1986.
The sampled clocking system adopted in the sampled servo system will be explained in FIGS. 2 and 3. FIG. 3 shows in block diagram the clocking circuit, and FIG. 2 shows the signals on the timing chart. In operation, as a light beam spot traces the track center 7, an optical sensor (not shown) produces a signal S1 (FIG. 2B) in terms of a change in the reflected light intensity. The signal S1 is fed through a peak detector 10, which then produces a signal S2 (FIG. 2C) indicative of the peak position of S1, i.e., the pit position. The peak detector 10 is realized using a differentiation circuit, for example.
The sampled clocking system resides in the method of dividing the interval of two contiguous clock pits 6 equally into N.sub.1 time-slots and placing N.sub.1 clock pulses in them. A clock pit extractor 11 is used to pick up from among the signal S1 a signal S3 (FIG. 2D) derived from the clock pit 6, and a PLL (Phase Locked Loop) circuit 12 is used to generate a clock signal S4 with an N.sub.1 -times frequency and in synchronism with S3. The servo area 2 is given a violation code pattern of modulation for the pit arrangement so that the pits do not appear in the data area 3. The clock pit extractor 11 can be realized in such a manner of pattern matching based on the measurement of the time interval between pits. The PLL circuit 12 has basically the same arrangement as a general frequency synthesizer, including a phase comparator (phase detector) 13, a low-pass filter 14, a VCO (Voltage Controlled Oscillator) 15, and a 1/N.sub.1 (N.sub.1 is an integer) frequency divider 16. The PLL circuit 12 produces the clock signal S4 with a frequency N.sub.1 times that of the clock pit pulse signal S3, and the S4 pulses divide one data segment 4 into equal N.sub.1 time-slots accurately even in the presence of eccentricity of the disk or fluctuation of the rotation speed.